A dynamic reconfigurable architecture for hybrid spiking and convolutional FPGA-based neural network designs

This work presents a dynamically reconfigurable architecture for Neural Network (NN) accelerators implemented in Field-Programmable Gate Array (FPGA) that can be applied in a variety of application scenarios. Although the concept of Dynamic Partial Reconfiguration (DPR) is increasingly used in NN accelerators, the throughput is usually lower than pure static designs. This work presents a dynamically reconfigurable energy-efficient accelerator architecture that does not sacrifice throughput performance. The proposed accelerator comprises reconfigurable processing engines and dynamically utilizes the device resources according to model parameters. Using the proposed architecture with DPR, different NN types and architectures can be realized on the same FPGA. Moreover, the proposed architecture maximizes throughput performance with design optimizations while considering the available resources on the hardware platform. We evaluate our design with different NN architectures for two different tasks. The first task is the image classification of two distinct datasets, and this requires switching between Convolutional Neural Network (CNN) architectures having different layer structures. The second task requires switching between NN architectures, namely a CNN architecture with high accuracy and throughput and a hybrid architecture that combines convolutional layers and an optimized Spiking Neural Network (SNN) architecture. We demonstrate throughput results from quickly reprogramming only a tiny part of the FPGA hardware using DPR. Experimental results show that the implemented designs achieve a 7× faster frame rate than current FPGA accelerators while being extremely flexible and using comparable resources

Open the box of digital neuromorphic processor: Towards effective algorithm-hardware co-design

Sparse and event-driven spiking neural network (SNN) algorithms are the ideal candidate solution for energy-efficient edge computing. Yet, with the growing complexity of SNN algorithms, it isn't easy to properly benchmark and optimize their computational cost without hardware in the loop. Although digital neuromorphic processors have been widely adopted to benchmark SNN algorithms, their black-box nature is problematic for algorithm-hardware co-optimization. In this work, we open the black box of the digital neuromorphic processor for algorithm designers by presenting the neuron processing instruction set and detailed energy consumption of the SENeCA neuromorphic architecture. For convenient benchmarking and optimization, we provide the energy cost of the essential neuromorphic components in SENeCA, including neuron models and learning rules. Moreover, we exploit the SENeCA's hierarchical memory and exhibit an advantage over existing neuromorphic processors. We show the energy efficiency of SNN algorithms for video processing and online learning, and demonstrate the potential of our work for optimizing algorithm designs. Overall, we present a practical approach to enable algorithm designers to accurately benchmark SNN algorithms and pave the way towards effective algorithm-hardware co-design

COW: A Co-evolving Memetic Wrapper for Herb-Herb Interaction Analysis in TCM Informatics

Traditional Chinese Medicine (TCM) relies heavily on interactions between herbs within prescribed formulae. However, given the combinatorial explosion due to the vast number of herbs available for treatment, the study of herb-herb interactions by pure human analysis is impractical, with computer aided analysis computationally expensive. Thus feature selection is crucial as a pre-processing step prior to herb-herb interaction analysis. In accord with this goal, a new feature selection algorithm known as a Co-evolving Memetic Wrapper (COW) is proposed: COW takes advantage of recent developments in genetic algorithms (GAs) and meme tic algorithms (MAs). evolving appropriate feature subsets for a given domain. As part of preliminary research. COW is demonstrated to he effective in selecting herbs in the TCM insomnia dataset. Finally, possible future applications of COW are examined, both within TCM research and in broader data mining contexts

A co-evolving memetic wrapper for prediction of patient outcomes in TCM informatics

Traditional Chinese medicine (TCM) relies on the combined effects of herbs within prescribed formulae. However, given the combinatorial explosion due to the vast number of herbs available for treatment, the study of these combined effects can become computationally intractable. Thus feature selection has become increasingly crucial as a pre-processing step prior to the study of combined effects in TCM informatics. In accord with this goal, a new feature selection algorithm known as a co-evolving memetic wrapper (COW) is proposed in this paper. COW takes advantage of recent research in genetic algorithms (GAs) and memetic algorithms (MAs) by evolving appropriate feature subsets for a given domain. Our empirical experiments have demonstrated that COW is capable of selecting subsets of herbs from a TCM insomnia dataset that shows signs of combined effects on the prediction of patient outcomes measured in terms of classification accuracy. We compare the proposed algorithm with results from statistical analysis including main effects and up to three way interaction terms and show that COW is capable of correctly identifying the herbs and herb by herb effects that are significantly associated to patient outcome prediction

Receiver-Sensitivity Control for Energy-Efficient IoT Networks

To increase energy efficiency of receiver-dominated nodes in IoT networks, we introduce Receiver-Sensitivity Control (RSC). RSC enables a trade-off between communication range and reception efforts. This trade-off is achieved through multiple receiver-sensitivity levels that can be adjusted at run time. The receiver can operate on lower sensitivity levels with reduced power consumption and conserve energy if the received signal quality is sufficiently high or otherwise use higher sensitivity levels to avoid packet re-transmissions. We evaluate the technique in a simulation of a realistic network scenario. The results show substantial energy savings of about 10-20% for better-than-worstcase channel conditions

A Binary Classifier Using SNP Data for Prediction of Phenotypic Outcomes in Hanwoo (Korean) Cattle

Korean 'Hanwoo' cattle are prized for their high marbling ability and meat quality. Classically, these cattle possess a homogeneous yellow coat colouring, with farmers believing that 'Hanwoo' with white spotted coats are crossbred and therefore unacceptable for breeding purposes. In this study we first attempted to determine if the coat spots were due to a non-'Hanwoo' genetic background or, alternatively, if the trait is intrinsic to the breed. By genotyping 232 (136 spotted) animals from half-sib families on the Illumina Bovine 50K SNP array, we compared the genotyped Hanwoo to other unrelated 'Hanwoo' and European taurine breeds using principal component analysis. Results showed no evidence of crossbreeding in the spotted animals. A differential evolution algorithm was then used to evolve a classifier for the trait which selected 12 SNP with an accuracy of ~82% in separating individuals; further investigation using only haplotypes inherited from the sires resulted in a marked improvement to ~92% accuracy for these 12 SNP. This research highlights the potential for using these SNP as genetic markers to either entirely remove the trait from the population in the long term or manage matings so that the trait is not expressed in the offspring

Receiver Design with an Adjustable Energy-Signal-Quality Trade-off for IoT Networks

The energy efficiency of an Internet-of-Things (IoT) receiver can be improved by introducing an adjustable trade-off between signal-quality and energy consumption. In good channel conditions, the receiver can be set to consume less energy per bit, without compromising signal quality in bad channel conditions. We propose a system-level receiver design that enables adequate configuration and combination of signal-quality and energy trade-offs in multiple receiver components. Co-design of all components is essential. We identify the most energy-efficient configurations in our system-level design under different channel conditions. With those configurations, the proposed receiver outperforms a state-of-the-art adjustable receiver with only an adjustable analog front end by several tens of percent in energy per successfully received bit and by 2x in energy-sensitivity configuration range. To show the efficacy of the proposed approach, we integrate a model of the proposed design into the OMNeT++ simulator and show the benefits on an environmental monitoring scenario. In this scenario, we report up to 6x energy savings for the entire transceiver compared to the conventional transceiver design without adjustable receiver

Understanding the impact of circuit-level inaccuracy on sensor network performance

Energy efficiency is of paramount importance in designing low-power wireless sensor nodes. Approximate computing is a new circuit-level technique for reducing power consumption. However, the gain in power by applying this technique is achieved at the cost of computational errors. The impact of such inaccuracies in the circuit level of a radio transceiver chip on the performance of Wireless Sensor Networks (WSNs) has not yet been explored. The applicability of such low-power chip design techniques depends on the overall energy gain and their impact on the network performance. In this paper, we analyze various inaccuracy fields in a radio chip, and quantify their impact on the network performance, in terms of packet latency, goodput, and energy per bit. The analysis is supported by extensive network simulations. The outcome can be used to investigate in which WSN application scenarios such power reduction techniques at circuit level can be applied, given the network performance and energy consumption requirements

An Event-Driven Recurrent Spiking Neural Network Architecture for Efficient Inference on FPGA

Spiking Neural Network (SNN) architectures are promising candidates for executing machine intelligence at the edge while meeting strict energy and cost reduction constraints in several application areas. To this end, we propose a new digital architecture compatible with Recurrent Spiking Neural Networks (RSNNs) trained using the PyTorch framework and Back-Propagation-Through-Time (BPTT) for optimizing the weights and the neuron’s parameters. Our architecture offers high software-to-hardware fidelity, providing high accuracy and a low number of spikes, and it targets efficient and low-cost implementations in Field Programmable Gate Arrays (FPGAs). We introduce a new time-discretization technique that uses request-acknowledge cycles between layers to allow the layer’s time execution to depend only upon the number of spikes. As a result, we achieve between 1.7x and 30x lower resource utilization and between 11x and 61x fewer spikes per inference than previous SNN implementations in FPGAs that rely on on-chip memory to store spike-time information and weight values. We demonstrate our approach using two benchmarks: MNIST digit recognition and a realistic radar and image sensory fusion for cropland classifications. Our results demonstrate that we can exploit the trade-off between accuracy, latency, and resource utilization at design time. Moreover, the use of low-cost FPGA platforms enables the deployment of several applications by satisfying the strict constraints of edge machine learning devices